TSMC Shows New Nodes

Making a chip starts with printing tiny patterns onto silicon, like projecting a stencil onto a wafer with light. On April 22 in Santa Clara, Taiwan Semiconductor Manufacturing Co. said its next A13 and N2U processes can keep shrinking chips without using ASML’s newest High-NA extreme ultraviolet tools through 2029. (pr.tsmc.com) TSMC said A13 is a direct shrink of its A14 node, which the company announced in 2025, and that A13 is scheduled for production in 2029. The company said A13 cuts chip area by 6% versus A14 and keeps A14 design rules backward compatible so customers can move designs over faster. (pr.tsmc.com) TSMC also introduced N2U, an added version of its 2-nanometer family aimed at 2028 production. The company said N2U can deliver 3% to 4% higher speed or 8% to 10% lower power than N2P, with a 1.02x to 1.03x gain in logic density. (pr.tsmc.com) The expensive tool in question is ASML’s High-NA EUV scanner, a newer version of the light-based machine used to draw the smallest features on advanced chips. TSMC Deputy Co-Chief Operating Officer Kevin Zhang told reporters the company has no current plan to use those machines in production through 2029. (bloomberg.com) Bloomberg reported those High-NA systems cost more than €350 million, or about $410 million, each. Electronics Weekly reported Zhang said TSMC can still “harvest the benefit from current EUV” through 2029, pointing to more gains from existing equipment rather than a near-term jump to ASML’s newest platform. (bloomberg.com) (electronicsweekly.com) That matters because TSMC is the world’s largest contract chipmaker, and its process choices shape the equipment plans of the rest of the industry. Bloomberg said TSMC is ASML’s largest customer, so delaying High-NA adoption pushes out one of the clearest commercial tests for ASML’s newest machine. (bloomberg.com) TSMC’s message was not that lithography no longer matters, but that it can still squeeze more performance, power savings, and density from its current extreme ultraviolet tools by changing both the manufacturing process and the chip design together. The company used that approach, which it calls design-technology co-optimization, to describe both A13 and N2U. (pr.tsmc.com) The company paired that roadmap with packaging upgrades for artificial intelligence chips, which now depend on connecting many dies and stacks of high-bandwidth memory inside one package. TSMC said a 14-reticle CoWoS package that can integrate about 10 large compute dies and 20 HBM stacks is slated for production in 2028, with larger versions planned for 2029. (electronicsweekly.com) ASML and rivals such as Intel still have reasons to keep pushing High-NA, because the tool is designed to make future patterning steps simpler and more precise at the smallest geometries. TSMC’s update instead set a date on a narrower claim: for its own roadmap, the company says today’s EUV machines can carry A13 and N2U into production before the High-NA handoff arrives. (bloomberg.com) (pr.tsmc.com)