AMD ramps EPYC Venice 2nm

AMD said on May 21 that its next-generation 6th Gen EPYC processor, codenamed “Venice,” is ramping production in Taiwan on Taiwan Semiconductor Manufacturing Co’s 2nm process technology. The company said Venice is the first high-performance computing product in the industry to reach production ramp on TSMC’s advanced 2nm node. AMD also said it plans future production at TSMC’s Arizona fabrication facility. The announcement gives AMD a new manufacturing milestone in its server CPU roadmap as chipmakers race to secure capacity on the most advanced process nodes for AI and data-center workloads. TSMC says its N2 technology started volume production in the fourth quarter of 2025 and uses first-generation nanosheet transistor technology. ### What exactly did AMD announce about Venice? (amd.com) AMD said Venice has entered “production ramp,” a step beyond the earlier silicon milestone the company disclosed in April 2025. At that time, AMD said Venice had become its first TSMC N2 product to reach a silicon milestone and was on track to launch in 2026. (tsmc.com) The May 21 release also introduced another product name tied to the same node transition. AMD said “Verano,” a follow-on to Venice, will use LPDDR integration aimed at rising memory demand in agentic AI workloads. ### Why does the 2nm node matter here? TSMC says N2 is its 2nm-class process and began volume production in 4Q25. (ir.amd.com) The foundry says the node uses gate-all-around nanosheet transistors and is designed to improve performance, power consumption and density over prior 3nm technology. AMD framed Venice as a high-performance computing part rather than a consumer chip. (amd.com) That matters because EPYC is AMD’s data-center CPU line, where gains in power efficiency, density and performance affect cloud, enterprise and AI infrastructure deployments. AMD said demand for accelerated AI infrastructure was one driver behind the milestone. (tsmc.com) ### What is Arizona’s role in this plan? AMD said future Venice production is planned for TSMC’s fabrication facility in Arizona. The company had already said in April 2025 that it had completed bring-up and validation of 5th Gen EPYC products at TSMC’s Arizona site. (ir.amd.com) TSMC says its Arizona investment has expanded to $165 billion and now includes plans for six wafer fabs, two advanced packaging facilities and an R&D team center in Phoenix. That makes Arizona relevant not only as a backup location, but as part of TSMC’s broader U.S. manufacturing buildout. ### Does this mean AMD is shifting away from Taiwan? AMD said Venice is ramping first in Taiwan, and its statement described Arizona as a future production site rather than the initial location. (ir.amd.com) TSMC remains the supplier at both sites, which means AMD is broadening geography within the same foundry relationship, not changing foundries. (tsmc.com) TSMC’s own materials still describe N2 as part of its high-performance computing platform and position the company as the provider of the process technology behind the rollout. ### What comes next on the roadmap? AMD said in April 2025 that Venice was on track to launch in 2026, and the May 21 production-ramp announcement did not give a narrower release date. (amd.com) The next visible milestones are product launch details from AMD and any confirmation that Venice output has expanded to TSMC’s Arizona facility. (ir.amd.com) (tsmc.com)