Siemens Tessent spotlight

Chip designers are pushing more test and security work earlier in the design cycle, and Siemens is pitching Tessent as the software stack to do both in one flow. (siemens.com) Tessent is Siemens EDA’s portfolio for design-for-test, the circuitry and software engineers add so a chip can be checked for defects before and after it ships. Siemens says the suite is built to cut design complexity, speed time-to-market and extend test into debug, monitoring and analytics after manufacturing. (siemens.com) The product lineup spans scan test, memory test, built-in self-test, boundary scan, embedded analytics and multi-die test. Siemens says tools including TestKompress, ScanPro, FastScan and RTL Pro share a common flow aimed at improving coverage, reducing test data volume and lowering manufacturing test cost. (siemens.com) That matters as system-on-chip designs pack in more logic, more software and more chiplets, which makes failures harder to isolate and fixes more expensive late in the process. Siemens said in its October 9, 2023 launch of Tessent RTL Pro that customers need to identify testability issues earlier and automate insertion of test logic at the register-transfer level, before synthesis. (siemens.com) Siemens is also tying test more tightly to silicon lifecycle management, its term for collecting and analyzing chip data from design through field use. The company says Tessent now covers manufacturing test, system debug, yield analysis, in-life monitoring, safety and security under one platform. (siemens.com; siemens.com) Security is a bigger part of that pitch because test ports can become attack paths if they stay open after shipment. Siemens says Tessent safety and security tools are designed to automate controls for authentication, communication protection and device lifecycle management while helping customers meet industry standards and regulations. (siemens.com) Partners are building around that opening. Crypto Quantique says it integrates its security intellectual property directly into Siemens Tessent design-for-test and IEEE 1687 IJTAG flows so test access can stay available for lifecycle monitoring without leaving ports exposed. (cryptoquantique.com) For engineering services firms, that creates a sellable layer above the software license: test-readiness audits, design-for-test insertion, verification acceleration, safety compliance work and post-silicon debug support. Siemens’ own materials describe Tessent as an automation platform for hierarchical design-for-test, analytics and validation, the kind of work many chip teams still outsource in peak periods. (siemens.com; siemens.com) The commercial logic is straightforward: the more chipmakers want test, debug and security handled as one continuous workflow, the more valuable the firms become that can wire Tessent into real projects quickly. Siemens’ message is that test is no longer a factory checkpoint; it is becoming part of how chips are designed, validated and managed over their full life. (siemens.com; siemens.com)