CoWoS/CoPoS equipment orders reshuffled as TSMC packaging allocations shift; EDA tie‑ups emerge

Advanced packaging is the step that bolts multiple chips and memory stacks into one module, and TSMC’s equipment orders are being reshuffled as one supplier fights a trade-secrets case. (digitimes.com) (finance.biggo.com) Grand Process Technology said on April 23 that it had filed a lawsuit over suspected trade-secret infringement by a former executive and that the case is under judicial investigation. The company also said it had found no evidence that critical equipment secrets had flowed to China. (finance.biggo.com) DigiTimes reported on April 24 that the fallout is affecting allocations for TSMC’s chip-on-wafer-on-substrate, or CoWoS, and chip-on-panel-on-substrate, or CoPoS, packaging equipment. The report described order shifts tied to turmoil at a Taiwanese equipment maker in TSMC’s packaging supply chain. (digitimes.com) CoWoS is the packaging method TSMC uses now for many artificial-intelligence chips, while CoPoS is the panel-based format it is developing to fit larger processors more efficiently. TSMC Chairman and Chief Executive C.C. Wei said on April 16 that CoWoS remains the company’s primary advanced-packaging approach. (trendforce.com) TrendForce, citing supply-chain sources, said TSMC’s CoPoS pilot line completed major equipment installation in February and is expected to finish full-line setup by June. The same report said volume production is broadly expected in 2028 or 2029. (trendforce.com 1) (trendforce.com 2) TSMC’s packaging buildout is large enough that equipment timing now matters beyond one supplier. TrendForce said institutional estimates put CoWoS capacity at roughly 115,000 to 140,000 wafers per month by the end of 2026, rising to about 170,000 in 2027. (trendforce.com) At the same time, Cadence is trying to reduce a different bottleneck: the software and verified building blocks needed to design AI chips fast enough for those packaging lines. On April 22, Cadence said it expanded its TSMC collaboration to deliver IP, certified flows and signoff-ready infrastructure for N3, N2, A16 and A14. (cadence.com) Cadence said the work covers digital, custom and analog, 3D-integrated-circuit and signoff platforms, plus “agent-ready” flows that use AI to optimize power, performance and area. TSMC’s Aveek Sarkar said the partnership is meant to help customers use the company’s latest process technologies and 3DFabric packaging. (cadence.com) TSMC’s own technology pages show why that timing matters. N2 entered volume production in the fourth quarter of 2025, while N2P is scheduled for volume production in the second half of 2026 and A16 is positioned for high-performance computing and AI. (tsmc.com 1) (tsmc.com 2) TSMC also said in April that its 2026 capital spending will be $52 billion to $56 billion, with 10% to 20% going to advanced packaging, testing, mask production and related areas. That leaves the company trying to expand physical packaging capacity even as its design ecosystem pushes more AI chips toward tapeout. (trendforce.com) The near-term story is not that TSMC has changed its packaging roadmap. It is that one legal dispute at a tool supplier and one EDA alliance expansion landed in the same week that TSMC is trying to scale both the factory floor and the design stack for AI silicon. (finance.biggo.com) (cadence.com)