TPU demand strains TSMC capacity

Taiwan’s Commercial Times reported) that HBM4 suppliers are redesigning base‑die components for next‑gen stacks, a technical revision that could push HBM4 shipments back roughly one quarter and lead Nvidia to trim Rubin wafer starts. Industry researcher TrendForce projected) that HBM4 mass production would not reach volume until the end of Q1 2026 after specification upgrades, while separate TrendForce reporting names Samsung and SK hynix as lead Rubin suppliers with shifting share forecasts. (trendforce.com) Analysts have flagged advanced‑packaging (CoWoS) as the pinch point: a Morgan Stanley note cited in market reports estimated Nvidia could book roughly 60% of 2026 CoWoS wafer slots (~595k wafers), squeezing peers’ access. (astutegroup.com) Multiple supply‑chain writeups say Google’s TPU volume plans were revised: public reporting and research notes indicate 2026 TPU forecasts were discussed in the 3M–4M unit range and some runs trimmed amid CoWoS constraints. (moomoo.com) Digitimes reported) that Nvidia conducted audits at Samsung’s Cheonan packaging campus, signaling active qualification work to diversify HBM4 sourcing and validate advanced packaging for Rubin‑class modules. Nvidia’s DGX product funnel shows active reservation and delivery management: Nvidia’s developer forum confirmed DGX Spark reservation waves and third‑party partners list DGX B200/H100 offerings, while vendor pages detail DGX B200 specs and rack power footprints that enterprises must provision when locking systems. (forums.developer.nvidia.com) Industry notes also point to a concentrated HBM4 supplier landscape: reporting suggests SK hynix and Samsung will account for the majority of early HBM4 bit output in 2026, with some narratives excluding Micron from initial Rubin design wins. (trendforce.com)