Jane Street's multi‑horizon FPGA stack

Jane Street’s name moved through trading and hardware circles this week after social posts described a layered execution stack: ultra-fast FPGA logic at the edge, richer models deeper in the system, and strict separation between the two. The firm does not publicly spell out a “multi-horizon FPGA stack” in those exact words. But Jane Street’s own engineering materials say it uses FPGA accelerators at the lowest level, handles millions of multicast messages per second on a single core, and builds machine-learning systems for microsecond-scale trading. Reuters reported on April 24 that Jane Street generated a record $39.6 billion in net trading revenue in 2025, outpacing major rivals and several Wall Street banks. That figure is not proof of any one hardware design, but it explains why engineers study the firm’s public comments for clues about how it organizes latency-sensitive systems. ### Where does the FPGA claim come from? (janestreet.com) Jane Street’s own performance-engineering page says, “At the lowest level, we use FPGA accelerators as a way of achieving performance that can’t be gotten on CPUs alone.” The same page says the firm is “shaving nanoseconds off the critical path in a trading system,” while separately describing machine-learning infrastructure built for “microsecond-scale trading.” That matters because it gives three public anchors for the social-media discussion: FPGA at the lowest layer, nanosecond attention to the critical path, and slower but still latency-sensitive model layers above it. (money.usnews.com) The firm does not publish a full production diagram, so any exact stack map beyond those points is inference from its published descriptions and outside commentary. ### Why do traders split the system across time horizons? (janestreet.com) Jane Street’s public wording points to different jobs being done at different speeds. The firm says packet-processing systems must handle “millions of multicast messages per second on a single core,” and that its models drive “microsecond-scale trading,” a distinction that supports the idea of separating immediate market-response logic from heavier valuation or prediction code. (janestreet.com) In practice, that usually means the fastest layer answers only narrow questions: Is the signal valid, is the price inside a bound, should the order be sent, canceled or ignored. More complex work—fair-value estimation, inventory balancing, cross-venue optimization, or model updates—can run outside that nanosecond path because every extra branch, memory lookup or software hop adds delay and jitter. That architecture is consistent with Jane Street’s public emphasis on determinism, tail events and custom tooling. (janestreet.com) ### Why not put the whole strategy on the FPGA? Jane Street’s engineering pages describe FPGAs as one part of a broader performance stack, not a complete replacement for software systems. The firm also highlights distributed systems, state-machine replication, GPUs, custom compilers and internal tools, suggesting that low-latency trading is split across several compute domains rather than collapsed into one device. That division reflects a common engineering trade-off. (janestreet.com) FPGA logic can deliver deterministic speed for small, fixed decision loops, while CPUs and GPUs are better suited to code that changes often, uses larger state, or depends on more elaborate models. Jane Street’s open-source Hardcaml work and FPGA-focused blog posts show it invests in hardware design productivity as well as raw speed, which fits a model where hardware is used selectively, not everywhere. ### What is the useful takeaway for execution teams? Jane Street’s public materials support one clear design lesson: keep the hottest path small. The firm says its packet systems focus on determinism and tail events, and its FPGA layer is reserved for performance CPUs cannot reach alone. For execution teams, that argues for a hard boundary between nanosecond decision code and richer valuation layers. The fastest path should consume precomputed thresholds, simple state and tightly bounded logic. (janestreet.com) The slower layers can do the expensive work—modeling, re-pricing, inventory logic and learning—then feed compact instructions into the edge layer. That is an inference from Jane Street’s published architecture cues, not a verbatim company blueprint. Jane Street’s February 2026 FPGA challenge results, its Hardcaml materials and its Signals and Threads episodes on reconfigurable hardware are the most concrete public places to watch for further detail from the firm itself. (blog.janestreet.com) (janestreet.com)