Packaging, not wafers, is the choke point
The semiconductor bottleneck is shifting from wafer fabs to advanced packaging, because leading buyers like Nvidia have locked much of TSMC’s premium packaging capacity — leaving the next scarcity layer in assembly and integration. That makes packaging capacity, geographic footprint and advanced packaging technologies strategic levers for procurement teams, and it’s driving partners and rivals (including Intel) to pursue regional alternatives and new projects. (cnbc.com) (letsdatascience.com).
The shortage in artificial intelligence chips has moved one step later in the factory. Nvidia has reserved most of Taiwan Semiconductor Manufacturing Company’s top-end advanced packaging capacity, so the squeeze is no longer just making wafers but finishing them into usable processors. (cnbc.com) That finishing step is called advanced packaging. It is the stage where separate pieces of silicon and high-bandwidth memory are wired together into one module, the way a car factory bolts an engine, transmission, and electronics into one chassis. (cnbc.com) For artificial intelligence chips, packaging is not a plastic shell around a chip. Taiwan Semiconductor Manufacturing Company’s main method, called Chip on Wafer on Substrate, puts multiple chip pieces and memory on a shared base so signals travel faster and power loss stays lower. (cnbc.com) That matters because the biggest graphics processing units are no longer one giant slab of silicon. Nvidia and other designers increasingly split work across smaller chip pieces and then depend on packaging to make those pieces behave like one very large chip. (cnbc.com) Taiwan Semiconductor Manufacturing Company told CNBC its Chip on Wafer on Substrate capacity is growing at an 80% compound annual rate. Even with that pace, demand is rising so fast that Paul Rousseau, the company’s North America packaging head, said the numbers are growing “very substantially.” (cnbc.com) Most of that capacity still sits in Asia. CNBC reported that almost all advanced packaging for these artificial intelligence chips happens there, which means a chip can be fabricated in one place and still need to cross an ocean before it is finished. (cnbc.com) That geography is why the United States buildout is suddenly about more than wafer plants. Taiwan Semiconductor Manufacturing Company’s Arizona plan includes two advanced packaging facilities alongside six wafer fabrication plants and a research and development center. (cnbc.com) Intel is trying to turn that gap into a business. Intel says its Rio Rancho, New Mexico site opened in January 2024 as part of a $3.5 billion investment focused on advanced packaging, including its Foveros technology for stacking multiple chips together. (intel.com) Intel is also adding capacity in Malaysia. Malaysian officials said in March 2026 that Intel’s advanced packaging complex and assembly manufacturing operations there are expected to begin later this year. (freemalaysiatoday.com) So the new contest is not just who can etch the best chip. It is who can package the most high-bandwidth memory, chip pieces, and substrates in the right region, at the right time, before the next buyer locks up the line. (cnbc.com)
