Siemens deploys AI for circuit design
Siemens has announced the integration of agentic AI into its Questa One platform to accelerate the design and verification of integrated circuits. The system uses AI-driven workflows combined with configurable human expertise to speed up the process of achieving trusted register-transfer level (RTL) sign-off. The tool is designed to be flexible to preserve clients' current technology investments.
The chip design industry is facing a major bottleneck. As chips become more complex, the rate of "first silicon success" has plummeted from 32% in 2020 to just 14% in 2024, with 75% of projects running behind schedule. There are not enough skilled verification engineers to keep up with the demand. The stage in question, register-transfer level (RTL) sign-off, is a critical pre-manufacturing step. It's not about what the chip does (functional signoff), but whether the design is structurally sound and ready for physical implementation. This involves painstaking checks for issues like unsynchronized signals between different clock domains. This push towards AI in Electronic Design Automation (EDA) is part of a wider industry shift some call 'EDA 4.0'. Siemens' competitors are also active in this space; Synopsys launched its DSO.ai platform in 2020, and Cadence offers a tool named Cerebrus AI. Siemens' Questa One platform integrates three types of purpose-built AI: analytical AI to identify data trends, predictive AI to accelerate decision-making, and generative AI to create new content like test plans. This goes beyond simple automation, aiming to augment the capabilities of human engineers. The "agentic" component of the AI is designed to act autonomously. It can optimize complex workflows and make decisions based on high-level design goals, moving beyond being just a passive tool. The system is built to work with a company's own secure design data, either on-premises or in the cloud. Ultimately, the goal is to close the verification productivity gap. Siemens claims early adopters have seen step-function gains in productivity across smart creation, regression, analysis, and debugging domains.
