Foundry pressure ramps up
Samsung’s HBM4E push and related foundry ties to NVIDIA are intensifying competition for memory and wafer capacity, while Tesla’s Terafab and other in‑house foundry moves are adding procurement complexity announced reported. Those pressures create windows for IP portability and multi‑sourcing strategies.
Samsung put sixth‑generation HBM4 into mass production at 11.7 Gbps and unveiled a physical HBM4E prototype that Samsung says targets 16 Gbps per pin and 4.0 TB/s aggregate bandwidth. (news.samsungsemiconductor.com) Samsung positioned itself as a “total AI solution” provider spanning memory, logic, foundry and advanced packaging and confirmed production roles tied to NVIDIA’s Vera Rubin platform, with NVIDIA noting Samsung will manufacture a new LPU for Rubin. (news.samsungsemiconductor.com) Samsung also showcased hybrid copper bonding (HCB) that it says enables 16+ HBM layers while cutting heat resistance by more than 20%, and promoted SOCAMM2 server memory as an industry‑first in mass production. (news.samsungsemiconductor.com) The HBM battlefield is already contested: TrendForce and industry reports show SK hynix, Micron and Samsung pushing higher per‑pin speeds (Micron samples above ~11 Gbps / ~2.8 TB/s were reported), tightening near‑term supply for next‑gen accelerators. (trendforce.com) Elon Musk’s terse X post “Terafab Project launches in 7 days” (March 14, 2026) followed Tesla comments from the January 28, 2026 earnings call that it may need a “gigantic chip fab,” and industry reporting has since pegged Terafab ambitions at roughly 100,000 wafer starts per month and a $20–25 billion capital scope with 100–200 billion chips per year cited in multiple writeups. (tomshardware.com) The net effect: NVIDIA’s Rubin ramp and Samsung’s vertical stack use up premium HBM and foundry slots while Terafab’s stated ambition signals another demand source, creating concrete windows for customers to insist on JEDEC‑compliant HBM interfaces, SOCAMM2 compatibility, and multi‑foundry porting paths to keep design timelines predictable. (nvidianews.nvidia.com)
