Technical Review Highlights Rise of Chiplet-Based Designs
A review in Semiconductor Engineering discusses the increasing adoption of chiplet-based hardware designs in the aerospace and automotive sectors. The modular approach allows for heterogeneous integration of compute, AI accelerators, and I/O on a single package. This trend is seen as a way to enable more flexible and scalable hardware for edge AI while potentially simplifying certification by isolating critical functions at the silicon level.
- The concept of disaggregating large systems into smaller, interconnected functions was first predicted in 1965 by Gordon Moore, who suggested it could be more economical than building large monolithic circuits. Early research into chiplet-like concepts was driven by DARPA programs such as COSMOS, initiated in 2007, and CHIPS (Common Heterogeneous Integration and IP Reuse). - To foster an open ecosystem, the Universal Chiplet Interconnect Express (UCIe) standard was established in March 2022. The consortium's founding members include AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC, with NVIDIA and Alibaba joining later. - The global chiplet market was valued between $8 billion and $9 billion in 2024 and is projected to reach over $200 billion by 2033, with some forecasts predicting a compound annual growth rate as high as 43.7%. - In the automotive sector, a chiplet approach can yield system-level cost reductions of 20-40% compared to monolithic SoCs by improving manufacturing yields and enabling the reuse of proven designs across different vehicle platforms. Chiplet-based designs must still meet stringent automotive qualifications such as AEC-Q100 and IATF 16949. - A primary technical challenge is ensuring each individual chiplet is a "Known Good Die" (KGD) before being integrated into a multi-die package. Testing is more complex than for monolithic chips, requiring multiple stages of verification to avoid scrapping an entire package due to a single faulty chiplet. - For aerospace applications, heterogeneous integration allows for combining chiplets made with different process technologies, such as radiation-hardened components alongside high-performance commercial computing elements, on a single package. This modularity can support the rigorous, systematic software verification processes required by avionics standards like DO-178C. - Advanced packaging is critical for chiplet integration, with 2.5D/3D packaging being the leading technology. These techniques involve intricate assembly on substrates or interposers, which introduces challenges in thermal management, signal integrity, and maintaining coplanarity across all the bonded microbumps.
