TSMC plans 80% packaging expansion

Advanced packaging is the part of chipmaking that used to feel secondary. Not anymore. For AI chips, the package is now where the hard engineering lives — linking giant compute dies to stacks of HBM memory and getting the whole thing to move data fast enough to matter. That is why TSMC’s latest message matters: the company is planning a huge packaging buildout through 2027, with roughly 80% growth from 2022 levels, because the bottleneck has shifted from the wafer fab to the package itself. (trendforce.com) ### What changed here? The fresh signal came out around TSMC’s April 2026 technology push, when industry coverage and investor notes converged on the same point: TSMC is no longer treating advanced packaging as support infrastructure. It is scaling CoWoS and other packaging lines as a frontline business, and the company has also started building its first advanced packaging footprint in Arizona while ramping more sites in Taiwan. (datacenterdynamics.com) ### What is CoWoS, really? CoWoS — chip-on-wafer-on-substrate — is the packaging method behind a lot of modern AI accelerators. It lets TSMC place a big logic die next to multiple HBM stacks on a silicon interposer, so the processor and memory can talk at very high bandwidth. Basically, if the GPU is the engine, CoWoS is the custom transmission that lets the engine actually deliver power to the road. (cnbc.com) ### Why is packaging the bottleneck now? Because AI chips got too big and too memory-hungry for old packaging methods. Foundries can keep shrinking transistors, but that does not solve the problem of connecting giant compute dies to enough HBM with low latency and manageable power. TSMC packaging head Paul Rousseau said the company’s most advanced packaging is growi(cnbc.com)o this step. Nvidia has already reserved most of TSMC’s top-end packaging capacity. (cnbc.com) ### How big is the expansion? The broad packaging number making the rounds is about 80% growth from 2022 to 2027. Separate estimates for CoWoS alone are even more aggressive in some reports, with capacity reaching roughly 1.3 million units in 2026 and 2 million in 2027, and wafer-start estimates rising into the 170,000 wafers-per-month range by 2027. Those figures c(cnbc.com) all point the same way — a very steep ramp. (trendforce.com) ### Why does this matter for customers? Because packaging scarcity changes product planning. If CoWoS slots are tight, chip designers cannot just finish a die and assume the rest will work itself out. They have to lock memory choices, reticle strategy, die partitioning, and package(trendforce.com) capacity makes that pressure even sharper for everyone else. (cnbc.com) ### Is this just about supply, or also profit? Also profit. TrendForce says advanced packaging reached about 10% of TSMC revenue in 2025 and could become a bigger profit driver as scale improves. The interesting twist is that packaging can be very lucrative without the same monster EUV tool burden as the most advanced front-end nodes. So TSMC is not only relieving a bottleneck — it is building a richer layer of the business. (trendforce.com) ### What is the catch? The catch is that capacity growth does not instantly erase scarcity. AI demand is still outrunning supply across packaging and HBM, and both have to line up for a finished accelerator to ship. So even with this expansion, the market is still living in a world where packaging reservations can shape who launches on time and who waits. (fusionww.com) ### Bottom line? TSMC is telling the market that the center of gravity in semiconductors has moved. The winning edge is no longer just who can make the smallest transistor. It is who can package giant AI chips at scale — and TSMC wants that chokepoint too.