Lattice demos PCIe FPGA trick
Lattice showed a Certus‑NX FPGA demo that lets a single connection handle two‑way PCIe communication and host‑to‑flash programming on NXP systems, a compact approach for hardware upgrades in low‑power, high‑performance appliances. The demo highlights options for simplifying hardware footprints where deterministic, hardware‑attached acceleration matters. The video and demo walkthrough are posted by Lattice for review. (x.com) (youtube.com)
A single cable is doing two jobs in Lattice’s latest hardware demo. The same Peripheral Component Interconnect Express link moves live data both ways and also lets the host processor rewrite flash memory on the other side. (youtube.com)(youtube.com) That sounds small until you picture the usual setup. Embedded boards often need one path for fast traffic and a separate path for programming, which means more traces, more connectors, and more board space. (latticesemi.com)(latticesemi.com) Peripheral Component Interconnect Express, usually shortened to PCI Express, is the short highway inside a computer or appliance that moves data between a processor and attached hardware. Lattice describes it as a standard built for high performance and software compatibility across computing and communications systems. (latticesemi.com)(latticesemi.com) A field-programmable gate array is a chip that can be rewired after manufacturing, more like a blank circuit board than a fixed-function processor. That makes it useful when a product needs custom hardware behavior without designing a new chip from scratch. (latticesemi.com)(latticesemi.com) The specific chip in this demo is Lattice’s Certus-NX family. Lattice says Certus-NX supports up to 65,000 logic cells, one lane of 5 gigabit-per-second Peripheral Component Interconnect Express, and packages as small as 6 by 6 millimeters. (latticesemi.com)(latticesemi.com) Flash memory is the non-volatile storage that keeps firmware when the power is off. On many embedded systems, updating that flash is how manufacturers ship bug fixes, board support packages, or entirely new boot images after hardware has already been installed. (nxp.com)(docs.nxp.com) NXP’s Layerscape boards are a good example of why that matters. NXP documents programming composite firmware images into Quad Serial Peripheral Interface flash on systems such as the FRWY-LS1046A, which is the kind of maintenance step engineers normally want to make as direct and reliable as possible. (nxp.com)(docs.nxp.com) Now the Lattice demo makes more sense. In the YouTube walkthrough, Lattice says its “full-bridge PCIe” intellectual property is running on a Certus field-programmable gate array with NXP host processors, and the field-programmable gate array shows up as a standard endpoint on the host side. (youtube.com)(youtube.com) From there, the host can do two different things over that same link. It can exchange normal Peripheral Component Interconnect Express traffic with the field-programmable gate array, and it can program attached flash memory without adding a separate programming cable in the demo setup. (youtube.com)(youtube.com) Lattice is pitching that as a footprint play as much as a speed play. Its Certus-NX evaluation board already centers on a 1-lane Generation 2 Peripheral Component Interconnect Express interface and on-board Serial Peripheral Interface boot flash, so combining communication and programming fits the board’s “connectivity platform” pitch. (latticesemi.com)(latticesemi.com) This kind of design is most attractive in boxes where the hardware has to react on schedule every time. Field-programmable gate arrays are often chosen in networking, storage, industrial, and appliance-style systems because a hardware data path can be more deterministic than sending the same work through general-purpose software. (latticesemi.com)(latticesemi.com) Lattice also leans hard on power and size in the Certus-NX line. The company says the family delivers up to 4 times lower power than similar field-programmable gate arrays and supports high-speed interfaces in compact packages, which is exactly the kind of tradeoff designers chase in fanless or space-constrained equipment. (latticesemi.com)(latticesemi.com) The demo does not announce a new chip or a new standard. It is a proof-of-concept showing that one Peripheral Component Interconnect Express connection can carry everyday traffic and also serve as the maintenance path for host-to-flash updates on an NXP-based platform. (youtube.com)(youtube.com) For engineers, that can mean fewer board-level parts and fewer external touch points. For product teams shipping low-power appliances, gateways, or embedded accelerators, it points to a cleaner way to keep hardware upgradable without giving up a direct hardware-attached data path. (latticesemi.com)(latticesemi.com)
