TSMC forecasts 70% annual 2nm capacity growth from 2026–2028 to meet AI demand
- Taiwan Semiconductor Manufacturing Co. said April 28 its 2-nanometer chip capacity will grow 70% a year from 2026 through 2028 as AI demand rises. - Senior vice president Cliff Hou said five fabs will be in 2nm volume production in 2026, including two in Hsinchu and three in Kaohsiung. - TSMC started N2 volume production in 4Q25, and packaging demand is still surging. (focustaiwan.tw)
Taiwan Semiconductor Manufacturing Co. said its 2-nanometer chip capacity will grow at a 70% compound annual rate from 2026 through 2028. (focustaiwan.tw) Cliff Hou, TSMC’s senior vice president and deputy co-chief operating officer, gave the forecast during the company’s 2026 Technology Symposium in Silicon Valley. He said five fabs will be in 2nm volume production this year. (focustaiwan.tw) (tsmc.com) Those five fabs include two plants in Hsinchu and three in Kaohsiung, according to Focus Taiwan’s report from April 28. TSMC’s own 2nm technology page says N2 volume production started in the fourth quarter of 2025. (focustaiwan.tw) (tsmc.com) A 2nm process is the recipe used to build the most advanced logic chips, the central computing pieces inside artificial intelligence accelerators, smartphone processors, and high-performance servers. TSMC says N2 is its first generation built with nanosheet transistors, a new structure aimed at improving performance and power use. (tsmc.com) TSMC is pairing that manufacturing ramp with newer variants. Its N2P process is scheduled for volume production in the second half of 2026, and its A16 process is positioned for high-performance computing and artificial intelligence workloads. (tsmc.com 1) (tsmc.com 2) The company used the same symposium cycle to unveil A13, a later-generation process it says is aimed at next-generation artificial intelligence, high-performance computing, and mobile chips. TSMC said April 22 that A13 volume production is planned for 2029. (tsmc.com) More wafer capacity does not remove every AI hardware constraint. TSMC says its CoWoS packaging is a key way to place processors and high-bandwidth memory side by side for artificial intelligence and supercomputing systems. (tsmc.com) That packaging step is still expanding quickly. CNBC reported on April 8 that Nvidia had reserved most of TSMC’s most advanced packaging capacity, and TSMC packaging executive Paul Rousseau said CoWoS capacity was growing at an 80% compound annual rate. (cnbc.com) TSMC is also pushing more of that packaging work into the United States. Reuters reported on April 22 that the company plans to open an advanced packaging plant in Arizona by 2029. (msn.com) The immediate picture is a faster 2nm buildout for the chips at the center of the AI spending wave, with the next squeeze still sitting in packaging and memory-heavy system assembly. (focustaiwan.tw) (cnbc.com)