TSMC to ship CoWoS SiPs spanning >14 reticles, capable of hosting up to 24 HBM5E stacks

Chip packaging is becoming the size limit for artificial intelligence processors, and Taiwan Semiconductor Manufacturing Co. just pushed that limit further out. On April 23, TSMC said its CoWoS packaging roadmap will extend beyond 14 reticles in 2029. (tsmc.com) A reticle is the stencil used to print a chip pattern on silicon, so “beyond 14 reticles” means a package much larger than a single chip exposure area. TSMC said a 14-reticle CoWoS package is slated for production in 2028 and can integrate about 10 large compute dies and 20 high-bandwidth memory stacks. (tsmc.com) CoWoS stands for Chip on Wafer on Substrate, a method that places logic chips and memory side by side on an interposer, which works like a dense wiring bridge. TSMC says the platform is being expanded specifically to fit more advanced nodes and more high-bandwidth memory for cloud, data-center, and high-end server chips. (tsmc.com) That shift changes what “bigger AI chips” means. Instead of one monolithic die getting ever larger, chip designers can spread compute across multiple dies and feed them with more stacked memory inside one package. (tsmc.com 1) (tsmc.com 2) TSMC paired the packaging update with a broader roadmap at its 2026 North America Technology Symposium in Santa Clara, where it also introduced its A13 process node. The company said A13 is scheduled for production in 2029, while an A12 platform enhancement and N2U, a 2-nanometer family option, are due in 2029 and 2028 respectively. (tsmc.com) TSMC’s latest earnings materials show why the company is leaning so hard into both leading-edge silicon and advanced packaging. In the first quarter of 2026, 3-nanometer technology contributed 25% of wafer revenue, and technologies at 7 nanometers and below accounted for 74% of total wafer revenue. (investor.tsmc.com) The company also reported first-quarter 2026 revenue of US$35.90 billion, up 40.6% from a year earlier, with gross margin at 66.2%. Those figures underline how much demand is being concentrated in the most advanced manufacturing and assembly steps. (investor.tsmc.com) (pr.tsmc.com) TSMC’s public materials did not, in the sources reviewed here, confirm the separate report that these beyond-14-reticle packages will host 24 HBM5E stacks. What TSMC did state directly is the 2028 step: 14 reticles, about 10 compute dies, and 20 HBM stacks. (tsmc.com) That makes the immediate story less about a single memory-generation label and more about the manufacturing direction. TSMC is telling customers that the next gains in AI systems will come from stitching together more silicon and more memory inside one package, then building enough factory capacity to ship it. (tsmc.com 1) (tsmc.com 2)