Morgan Stanley quiet on low‑latency
No new public disclosures emerged about Morgan Stanley’s low‑latency platform, FPGA work or kernel‑bypass deployments in this cycle — the firm’s silence likely reflects continued internal modernization rather than headline projects. Analysts still cite the bank positively for platform resilience and incremental upgrades. (insidermonkey.com)
Morgan Stanley posted a "Lead Low Latency Electronic Trading Network Engineer — VP" role (PT‑JR027246) for London on its external careers site 22 days ago. (ms.wd5.myworkdayjobs.com)) Multiple FPGA developer listings from Morgan Stanley during the past year specify Verilog/VHDL, Vivado synthesis, and experience building low‑latency electronic trading systems, and they place those hires inside an "Ultra‑Low Latency Connectivity" team responsible for global ULL platforms. (simplify.jobs)) Morgan Stanley publishes performance tooling publicly: Xpedite is an Apache‑2.0 non‑sampling profiler the firm maintains on GitHub specifically for measuring and optimising C++ ultra‑low‑latency and real‑time systems (the repo shows ~278 commits). (github.com)) A Morgan Stanley executive, Michael Gorbovitski (Executive Director), participated on a STAC FPGA panel on May 31, 2023 that focused on FPGA hardware acceleration and trading use cases, indicating continued engagement with FPGA vendor and research ecosystems. (docs.stacresearch.com)) Trade coverage of past platform work documents Speedway and Project Velocity upgrades that targeted pre‑trade risk checks down to the ~2 microsecond range in 2011, showing a historical emphasis on shaving microseconds from order paths. (tradersmagazine.com)) Industry commentary and recruitment coverage have repeatedly linked Morgan Stanley's Speedway and Project Velocity efforts to measurable gains in electronic trading competitiveness versus peers by the mid‑2010s, a narrative still cited in trade press and hiring notices. (efinancialcareers.com))
